In the manufacture of certain types of integrated circuits, such as high device density, dynamic random access memories (DRAMs), and static random access memories (SRAMs), it has been a common practice to use pump circuits in the IC substrate in order to generate bias voltages above the +5 volt Vcc IC supply voltage and below ground potential, or above and below the two rails of logic swing commonly used for switching the integrated circuit between two digital levels of logic. These large voltage swings beyond the two rails of logic are useful in optimizing the biasing and switching of memory circuits such as SRAMs and DRAMs fabricated within an integrated circuit chip.
For example, certain ones of the above identified SRAMs and DRAMs are fabricated on P-type substrates wherein active devices are formed by making N-type diffusions or ion implantations into the P-type substrate, thereby forming P-N junctions in the substrate which present a parasitic capacitance that must be compensated for during circuit operation. Thus, it has been a common practice to apply a negative potential to the P-type substrate to thereby reverse bias the above described P-N junctions to increase their depletion width and thereby decrease their junction capacitance accordingly. This has been done by applying a negative potential generated by the above pump circuits to the P-type substrate to in turn provide this reverse biasing effect. This biasing also improves MOS device threshold control.
One type of pump circuit which has been used to provide the above rail to rail switching and pumping action utilizes a ring oscillator cascaded to an output driver stage which is in turn capacitively coupled to drive the substrate below ground potential. Typically, the ring oscillator and the driver stage will include a plurality of complementary connected P-channel and N-channel MOS field effect transistors which are connected between input and output terminals for a given CMOS switching cell. Each such cell will normally include at least one P-channel MOS transistor and one N-channel MOS transistor connected in series between the Vcc power supply and ground potential. The gates of the P-channel and N-channel devices are connected to a common input terminal, and the drain of the P-channel device and the drain of the N-channel device are connected to a common output terminal.
A significant operational disadvantage characteristic of the above P-channel/N-channel two transistor cell is that one of the output P-channel or N-channel devices does not completely turn off before the other output device turns on. This in turn produces a so called crossing or crossover current which represents wasted power dissipation for the pump circuit. This operational disadvantage has in the past been mitigated to some degree by the use of so called long channel complementary transistors connected in series with the above P-channel and N-channel transistors, thereby converting the two transistor switching cell to a four transistor switching cell. These long channel MOS devices thus increased the impedance in series with the primary P-channel and N-channel MOS devices and thereby reduced the level of crossing current within the circuit. However, these long channel MOS devices in turn added a significant degree of parasitic capacitance in series with the primary P-channel and N-channel devices, and this in turn not only decreases frequency response of the pump circuit, but it also adds to the capacitive load driving requirements and power supply requirements for the pump circuit.
Accordingly, it is the solution to the above problems of crossover current and increased parasitic capacitance to which the present invention is directed.